The present invention relates to a multi-processor system, and more particularly to a system for transferring vector data between the processors of a parallel processing system.
In a parallel processing system, efficient communication between the processors is an important consideration especially when a plurality of processors must process vectors. It is therefor necessary to transfer the large amount of data between the processors efficiently.
U.S. Pat. No. 4,636,942 discloses a communication control circuit to monitor and control the data transfer between tightly coupled processors through a common register and a central or main memory using a semaphore register.
The semaphore register protects a common data resource from being simultaneously accessed by the tightly coupled processors of the system. The semaphore register also contains high speed hardware for software communication between the processors. Common parameters, such as scalar data, are transferred between the processors through the common register, and vector data is transferred through the central or main memory.
In the vector data transfer between the processors, the vector data is transferred through the central or main memory exclusively. In a parallel processing system, access to the central or main memory becomes concentrated as the number processes in the system increases. In some cases, the central memory cannot grant all access requests from the individual processors and therefor some processors must wait to be serviced. The processors thus denied access to the central memory are placed in a wait state and remain idle until their access requests are honored. When processors are made to wait for access to the central memory for the transfer of vector data, the system throughput is reduced because of increases in transfer overhead greatly reducing the overall performance of the parallel processing system.